The present invention relates to a semiconductor integrated circuit equipped with a mechanism for detecting any delay arising within the semiconductor integrated circuit and controlling the quantity of processing by an internal logic circuit per unit time length on the basis of the result of this detection.
Generally, the main reasons for an increase in delay arising within an LSI are a drop in voltage at the source of power supplied to the LSI and an increase in internal resistance of the LSI accompanying a temperature rise therein. The causes of a temperature rise in an LSI in turn include an increase in the LSI""s power consumption ensuing from increased processing within the LSI.
In recent years, attempts to achieve an even higher scale of integration and a still higher speed of processing have been made on LSIs, and in some cases the temperature of the operating LSI exceeds the normative higher limit beyond which the stability of the LSI""s operation may be lost unless the temperature rise is suppressed somehow from outside.
Referring to FIG. 8, a prior art temperature rise suppressing system comprises an MPU 81, which is a typical example of LSI embodying attempts to achieve a higher scale of integration and a higher speed of processing, a temperature sensor 82 for constantly measuring the surface temperature of the MPU 81, and an MPU control circuit 83 for receiving temperature information measured by the temperature sensor 82 and transmitting to the MPU 81 a control signal for controlling the operation of the MPU 81 according to this temperature information. Incidentally, the temperature sensor 82 is provided outside the MPU 81, for instance on the package of the MPU 81.
The control circuit 83 reduces the rate of operation of the MPU 81 per unit time length or suspends the operation of the MPU 81 according to its temperature rise. It also gives an instruction to a clock generator (not shown) to reduce the frequency of a clock to be supplied to the MPU 81.
Such a system can restrain, when the temperature of the MPU 81 has risen, power consumption by the MPU 81, heat generation by the MPU 81 and thereby to control the MPU 81 so that it can normally operate within its normative temperature range.
However, the prior art system of described above cannot utilize the full potential of the MPU 81 because there are differences between variations in delay length actually occurring in the MPU 81 and variations in delay length presumed from temperature changes in the MPU 81 detected by the sensor 82.
These differences invite a drop in the overall processing capacity of the MPU 81 per unit time length even when the stable operation of the MPU 81 is unlikely to be affected.
An object of the present invention is to provide a semiconductor integrated circuit equipped with an operation control mechanism capable of drawing upon the full capability of the semiconductor integrated circuit all the time.
According to an aspect of the present invention, there is provided a semiconductor integrated circuit which comprises an internal logic circuit, a delay detecting circuit which monitors changes in delay length within the semiconductor integrated circuit, and a central control circuit which controls the quantity of processing per unit time length by the internal logic circuit on the basis of changes in delay length monitored by the delay detecting circuit.